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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY pcie_rx_test IS
END pcie_rx_test;
ARCHITECTURE behavior OF pcie_rx_test IS
COMPONENT pcie_rx
PORT(
clk : IN std_logic;
frame : IN std_logic_vector(63 downto 0);
sof : IN std_logic;
eof : IN std_logic;
valid : IN std_logic;
read : OUT std_logic;
write : OUT std_logic;
complete : OUT std_logic;
data : OUT std_logic_vector(63 downto 0);
address : OUT std_logic_vector(63 downto 3);
tag : OUT std_logic_vector(4 downto 0);
remote : OUT std_logic_vector(15 downto 0);
bar0 : IN std_logic
);
END COMPONENT;
signal clk : std_logic := '0';
signal frame : std_logic_vector(63 downto 0) := (others => '0');
signal sof : std_logic := '0';
signal eof : std_logic := '0';
signal valid : std_logic := '0';
signal read : std_logic;
signal write : std_logic;
signal complete : std_logic;
signal data : std_logic_vector(63 downto 0);
signal address : std_logic_vector(63 downto 3);
signal tag : std_logic_vector(4 downto 0);
signal remote : std_logic_vector(15 downto 0);
signal bar0 : std_logic := '0';
constant clk_period : time := 10 ns;
constant ADDR_0 : std_logic_vector(63 downto 3) := std_logic_vector(to_unsigned(0, 61));
constant ADDR_1 : std_logic_vector(63 downto 3) := std_logic_vector(to_unsigned(1, 61));
constant ADDR_2 : std_logic_vector(63 downto 3) := std_logic_vector(to_unsigned(2, 61));
constant TAG_0 : std_logic_vector(4 downto 0) := "0" & x"0";
constant TAG_A : std_logic_vector(4 downto 0) := "0" & x"A";
constant TAG_B : std_logic_vector(4 downto 0) := "0" & x"B";
constant ID_0 : std_logic_vector(15 downto 0) := x"0000";
constant ID_A : std_logic_vector(15 downto 0) := x"AAAA";
constant ID_B : std_logic_vector(15 downto 0) := x"BBBB";
constant DATA_0 : std_logic_vector(63 downto 0) := x"0000000000000000";
constant DATA_A : std_logic_vector(63 downto 0) := x"AAAAAAAAAAAAAAAA";
constant DATA_B : std_logic_vector(63 downto 0) := x"BBBBBBBBBBBBBBBB";
signal test_fail : std_logic := '0';
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pcie_rx PORT MAP (
clk => clk,
frame => frame,
sof => sof,
eof => eof,
valid => valid,
read => read,
write => write,
complete => complete,
data => data,
address => address,
tag => tag,
remote => remote,
bar0 => bar0
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
bar0 <= '1';
wait for clk_period;
-- expect nothing
if read /= '0' or
write /= '0' or
complete /= '0' or
remote /= ID_0 then
test_fail <= '1';
end if;
-- read: addr = 1, tag = A, remote = A
frame <= "0" & "00" & "00000" &
x"00" &
"000000" & "0000000010" &
ID_A & "000" & TAG_A & x"FF";
sof <= '1';
eof <= '0';
valid <= '1';
wait for clk_period;
-- remote = A
if read /= '0' or
write /= '0' or
complete /= '0' or
remote /= ID_A then
test_fail <= '1';
end if;
frame <= ADDR_1(31 downto 3) & "000" & x"00000000";
sof <= '0';
eof <= '1';
valid <= '1';
wait for clk_period;
-- read: addr = 1, tag = A, remote = A
if read /= '1' or
write /= '0' or
complete /= '0' or
data /= DATA_0 or
address /= ADDR_1 or
tag /= TAG_A or
remote /= ID_A then
test_fail <= '1';
end if;
-- write: data = A, addr = 2
frame <= "0" & "10" & "00000" &
x"00" &
"000000" & "0000000010" &
ID_B & x"00" & x"FF";
sof <= '1';
eof <= '0';
valid <= '1';
wait for clk_period;
-- remote stays A
if read /= '0' or
write /= '0' or
complete /= '0' or
remote /= ID_A then
test_fail <= '1';
end if;
frame <= ADDR_2(31 downto 3) & "000" & DATA_A(63 downto 32);
sof <= '0';
eof <= '0';
valid <= '1';
wait for clk_period;
-- expect nothing
if read /= '0' or
write /= '0' or
complete /= '0' or
remote /= ID_A then
test_fail <= '1';
end if;
frame <= DATA_A(31 downto 0) & x"00000000";
sof <= '0';
eof <= '1';
valid <= '1';
wait for clk_period;
-- write: data = A, addr = 2
if read /= '0' or
write /= '1' or
complete /= '0' or
data /= DATA_A or
address /= ADDR_2 or
tag /= TAG_0 or
remote /= ID_A then
test_fail <= '1';
end if;
frame <= (others => '0');
sof <= '0';
eof <= '0';
valid <= '0';
wait for clk_period;
-- expect nothing
if read /= '0' or
write /= '0' or
complete /= '0' or
remote /= ID_A then
test_fail <= '1';
end if;
-- complete: length = 2x32b, data = A + B, tag = B
frame <= "0" & "10" & "01010" &
x"00" &
"000000" & "0000000100" &
ID_B & x"0004";
sof <= '1';
eof <= '0';
valid <= '1';
wait for clk_period;
-- expect nothing
if read /= '0' or
write /= '0' or
complete /= '0' or
remote /= ID_A then
test_fail <= '1';
end if;
frame <= ID_B & "000" & TAG_B & x"00" &
DATA_A(63 downto 32);
sof <= '0';
eof <= '0';
valid <= '1';
wait for clk_period;
-- nothing
if read /= '0' or
write /= '0' or
complete /= '0' or
remote /= ID_A then
test_fail <= '1';
end if;
frame <= DATA_A(31 downto 0) & DATA_B(63 downto 32);
sof <= '0';
eof <= '0';
valid <= '1';
wait for clk_period;
-- completion: data = A, tag = B
if read /= '0' or
write /= '0' or
complete /= '1' or
data /= DATA_A or
address /= ADDR_0 or
tag /= TAG_B or
remote /= ID_A then
test_fail <= '1';
end if;
frame <= (others => '0');
sof <= '0';
eof <= '0';
valid <= '0';
wait for clk_period;
-- nothing
if read /= '0' or
write /= '0' or
complete /= '0' or
remote /= ID_A then
test_fail <= '1';
end if;
frame <= DATA_B(31 downto 0) & x"01234567";
sof <= '0';
eof <= '1';
valid <= '1';
wait for clk_period;
-- completion: data = B, tag = B
if read /= '0' or
write /= '0' or
complete /= '1' or
data /= DATA_B or
address /= ADDR_0 or
tag /= TAG_B or
remote /= ID_A then
test_fail <= '1';
end if;
frame <= (others => '0');
sof <= '0';
eof <= '0';
valid <= '0';
wait for clk_period;
-- nothing
if read /= '0' or
write /= '0' or
complete /= '0' or
remote /= ID_A then
test_fail <= '1';
end if;
wait;
end process;
END;
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