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diff --git a/netfpga10g/hdl/pcie_wrapper.vhd b/netfpga10g/hdl/pcie_wrapper.vhd
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+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity pcie_wrapper is port (
+ pcie_clk_p : in std_logic;
+ pcie_clk_n : in std_logic;
+ reset25 : in std_logic;
+
+ clk125 : out std_logic;
+ reset125 : out std_logic;
+
+ pci_exp_rxn : in std_logic_vector(7 downto 0);
+ pci_exp_rxp : in std_logic_vector(7 downto 0);
+ pci_exp_txn : out std_logic_vector(7 downto 0);
+ pci_exp_txp : out std_logic_vector(7 downto 0);
+
+ rx_frame : out std_logic_vector(63 downto 0);
+ rx_sof : out std_logic;
+ rx_eof : out std_logic;
+ rx_valid : out std_logic;
+
+ tx_frame : in std_logic_vector(63 downto 0);
+ tx_sof : in std_logic;
+ tx_eof : in std_logic;
+ tx_half : in std_logic;
+ tx_valid : in std_logic;
+ tx_ready : out std_logic;
+
+ bus_dev_func : out std_logic_vector(15 downto 0);
+
+ max_read : out std_logic_vector(2 downto 0);
+ max_write : out std_logic_vector(2 downto 0);
+
+ interrupt : in std_logic;
+ interrupt_rdy : out std_logic;
+
+ bar0 : out std_logic
+);
+end pcie_wrapper;
+
+architecture arch of pcie_wrapper is
+
+ component pcie_core port (
+ pci_exp_rxn : in std_logic_vector(7 downto 0);
+ pci_exp_rxp : in std_logic_vector(7 downto 0);
+ pci_exp_txn : out std_logic_vector(7 downto 0);
+ pci_exp_txp : out std_logic_vector(7 downto 0);
+
+ sys_clk : in std_logic;
+ sys_reset_n : in std_logic;
+
+ refclkout : out std_logic;
+
+ trn_clk : out std_logic;
+ trn_reset_n : out std_logic;
+ trn_lnk_up_n : out std_logic;
+
+ trn_rd : out std_logic_vector(63 downto 0);
+ trn_rrem_n : out std_logic_vector(7 downto 0);
+ trn_rsof_n : out std_logic;
+ trn_reof_n : out std_logic;
+ trn_rsrc_dsc_n : out std_logic;
+ trn_rsrc_rdy_n : out std_logic;
+ trn_rbar_hit_n : out std_logic_vector(6 downto 0);
+ trn_rdst_rdy_n : in std_logic;
+ trn_rerrfwd_n : out std_logic;
+ trn_rnp_ok_n : in std_logic;
+ trn_rfc_npd_av : out std_logic_vector(11 downto 0);
+ trn_rfc_nph_av : out std_logic_vector(7 downto 0);
+ trn_rfc_pd_av : out std_logic_vector(11 downto 0);
+ trn_rfc_ph_av : out std_logic_vector(7 downto 0);
+ trn_rcpl_streaming_n : in std_logic;
+
+ trn_td : in std_logic_vector(63 downto 0);
+ trn_trem_n : in std_logic_vector(7 downto 0);
+ trn_tsof_n : in std_logic;
+ trn_teof_n : in std_logic;
+ trn_tsrc_dsc_n : in std_logic;
+ trn_tsrc_rdy_n : in std_logic;
+ trn_tdst_dsc_n : out std_logic;
+ trn_tdst_rdy_n : out std_logic;
+ trn_terrfwd_n : in std_logic ;
+ trn_tbuf_av : out std_logic_vector(3 downto 0);
+
+ cfg_do : out std_logic_vector(31 downto 0);
+ cfg_rd_wr_done_n : out std_logic;
+ cfg_di : in std_logic_vector(31 downto 0);
+ cfg_byte_en_n : in std_logic_vector(3 downto 0);
+ cfg_dwaddr : in std_logic_vector(9 downto 0);
+ cfg_wr_en_n : in std_logic;
+ cfg_rd_en_n : in std_logic;
+
+ cfg_err_cor_n : in std_logic;
+ cfg_err_cpl_abort_n : in std_logic;
+ cfg_err_cpl_timeout_n : in std_logic;
+ cfg_err_cpl_unexpect_n : in std_logic;
+ cfg_err_ecrc_n : in std_logic;
+ cfg_err_posted_n : in std_logic;
+ cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
+ cfg_err_ur_n : in std_logic;
+ cfg_err_cpl_rdy_n : out std_logic;
+ cfg_err_locked_n : in std_logic;
+ cfg_interrupt_n : in std_logic;
+ cfg_interrupt_rdy_n : out std_logic;
+ cfg_pm_wake_n : in std_logic;
+ cfg_pcie_link_state_n : out std_logic_vector(2 downto 0);
+ cfg_to_turnoff_n : out std_logic;
+ cfg_interrupt_assert_n : in std_logic;
+ cfg_interrupt_di : in std_logic_vector(7 downto 0);
+ cfg_interrupt_do : out std_logic_vector(7 downto 0);
+ cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
+ cfg_interrupt_msienable : out std_logic;
+
+ cfg_trn_pending_n : in std_logic;
+ cfg_bus_number : out std_logic_vector(7 downto 0);
+ cfg_device_number : out std_logic_vector(4 downto 0);
+ cfg_function_number : out std_logic_vector(2 downto 0);
+ cfg_status : out std_logic_vector(15 downto 0);
+ cfg_command : out std_logic_vector(15 downto 0);
+ cfg_dstatus : out std_logic_vector(15 downto 0);
+ cfg_dcommand : out std_logic_vector(15 downto 0);
+ cfg_lstatus : out std_logic_vector(15 downto 0);
+ cfg_lcommand : out std_logic_vector(15 downto 0);
+ cfg_dsn : in std_logic_vector(63 downto 0);
+
+ fast_train_simulation_only : in std_logic
+ );
+ end component;
+
+ signal sys_reset_n : std_logic;
+
+ signal trn_clk : std_logic;
+ signal trn_reset_n : std_logic;
+ signal trn_lnk_up_n : std_logic;
+
+ signal trn_rd : std_logic_vector(63 downto 0);
+ signal trn_rrem_n : std_logic_vector(7 downto 0);
+ signal trn_rsof_n : std_logic;
+ signal trn_reof_n : std_logic;
+ signal trn_rsrc_dsc_n : std_logic;
+ signal trn_rsrc_rdy_n : std_logic;
+ signal trn_rbar_hit_n : std_logic_vector(6 downto 0);
+ signal trn_rdst_rdy_n : std_logic;
+ signal trn_rerrfwd_n : std_logic;
+ signal trn_rnp_ok_n : std_logic;
+ signal trn_rfc_npd_av : std_logic_vector(11 downto 0);
+ signal trn_rfc_nph_av : std_logic_vector(7 downto 0);
+ signal trn_rfc_pd_av : std_logic_vector(11 downto 0);
+ signal trn_rfc_ph_av : std_logic_vector(7 downto 0);
+ signal trn_rcpl_streaming_n : std_logic;
+
+ signal trn_td : std_logic_vector(63 downto 0);
+ signal trn_trem_n : std_logic_vector(7 downto 0);
+ signal trn_tsof_n : std_logic;
+ signal trn_teof_n : std_logic;
+ signal trn_tsrc_dsc_n : std_logic;
+ signal trn_tsrc_rdy_n : std_logic;
+ signal trn_tdst_dsc_n : std_logic;
+ signal trn_tdst_rdy_n : std_logic;
+ signal trn_terrfwd_n : std_logic;
+ signal trn_tbuf_av : std_logic_vector(3 downto 0);
+
+ signal cfg_do : std_logic_vector(31 downto 0);
+ signal cfg_rd_wr_done_n : std_logic;
+ signal cfg_di : std_logic_vector(31 downto 0);
+ signal cfg_byte_en_n : std_logic_vector(3 downto 0);
+ signal cfg_dwaddr : std_logic_vector(9 downto 0);
+ signal cfg_wr_en_n : std_logic;
+ signal cfg_rd_en_n : std_logic;
+
+ signal cfg_err_cor_n : std_logic;
+ signal cfg_err_cpl_abort_n : std_logic;
+ signal cfg_err_cpl_timeout_n : std_logic;
+ signal cfg_err_cpl_unexpect_n : std_logic;
+ signal cfg_err_ecrc_n : std_logic;
+ signal cfg_err_posted_n : std_logic;
+ signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
+ signal cfg_err_ur_n : std_logic;
+ signal cfg_err_cpl_rdy_n : std_logic;
+ signal cfg_err_locked_n : std_logic;
+ signal cfg_interrupt_n : std_logic;
+ signal cfg_interrupt_rdy_n : std_logic;
+ signal cfg_pm_wake_n : std_logic;
+ signal cfg_pcie_link_state_n : std_logic_vector(2 downto 0);
+ signal cfg_to_turnoff_n : std_logic;
+ signal cfg_interrupt_assert_n : std_logic;
+ signal cfg_interrupt_di : std_logic_vector(7 downto 0);
+ signal cfg_interrupt_do : std_logic_vector(7 downto 0);
+ signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
+ signal cfg_interrupt_msienable : std_logic;
+
+ signal cfg_trn_pending_n : std_logic;
+ signal cfg_bus_number : std_logic_vector(7 downto 0);
+ signal cfg_device_number : std_logic_vector(4 downto 0);
+ signal cfg_function_number : std_logic_vector(2 downto 0);
+ signal cfg_status : std_logic_vector(15 downto 0);
+ signal cfg_command : std_logic_vector(15 downto 0);
+ signal cfg_dstatus : std_logic_vector(15 downto 0);
+ signal cfg_dcommand : std_logic_vector(15 downto 0);
+ signal cfg_lstatus : std_logic_vector(15 downto 0);
+ signal cfg_lcommand : std_logic_vector(15 downto 0);
+ signal cfg_dsn : std_logic_vector(63 downto 0);
+
+ signal pcie_clk : std_logic;
+begin
+ pcie_clk_ibuf : IBUFDS port map (
+ O => pcie_clk,
+ I => pcie_clk_p,
+ IB => pcie_clk_n
+ );
+
+ sys_reset_n <= not reset25;
+
+ trn_rdst_rdy_n <= '0';
+ trn_rnp_ok_n <= '0';
+ trn_rcpl_streaming_n <= '1';
+
+ trn_tsrc_dsc_n <= '1';
+ trn_terrfwd_n <= '1';
+
+ cfg_di <= (others => '0');
+ cfg_byte_en_n <= (others => '1');
+ cfg_dwaddr <= (others => '0');
+ cfg_wr_en_n <= '1';
+ cfg_rd_en_n <= '1';
+
+ cfg_err_cor_n <= '1';
+ cfg_err_cpl_abort_n <= '1';
+ cfg_err_cpl_timeout_n <= '1';
+ cfg_err_cpl_unexpect_n <= '1';
+ cfg_err_ecrc_n <= '1';
+ cfg_err_posted_n <= '1';
+ cfg_err_tlp_cpl_header <= (others => '0');
+ cfg_err_ur_n <= '1';
+ cfg_err_locked_n <= '1';
+ cfg_interrupt_n <= not interrupt;
+ cfg_pm_wake_n <= '1';
+ cfg_interrupt_assert_n <= '1';
+ cfg_interrupt_di <= (others => '0');
+ interrupt_rdy <= not cfg_interrupt_rdy_n;
+
+ cfg_trn_pending_n <= '1';
+ cfg_dsn <= (others => '0');
+
+ ep : pcie_core port map (
+ pci_exp_rxn => pci_exp_rxn,
+ pci_exp_rxp => pci_exp_rxp,
+ pci_exp_txn => pci_exp_txn,
+ pci_exp_txp => pci_exp_txp,
+
+ sys_clk => pcie_clk,
+ sys_reset_n => sys_reset_n,
+
+ refclkout => open,
+
+ trn_clk => trn_clk,
+ trn_reset_n => trn_reset_n,
+ trn_lnk_up_n => trn_lnk_up_n,
+
+ trn_rd => trn_rd,
+ trn_rrem_n => trn_rrem_n,
+ trn_rsof_n => trn_rsof_n,
+ trn_reof_n => trn_reof_n,
+ trn_rsrc_dsc_n => trn_rsrc_dsc_n,
+ trn_rsrc_rdy_n => trn_rsrc_rdy_n,
+ trn_rbar_hit_n => trn_rbar_hit_n,
+ trn_rdst_rdy_n => trn_rdst_rdy_n,
+ trn_rerrfwd_n => trn_rerrfwd_n,
+ trn_rnp_ok_n => trn_rnp_ok_n,
+ trn_rfc_npd_av => trn_rfc_npd_av,
+ trn_rfc_nph_av => trn_rfc_nph_av,
+ trn_rfc_pd_av => trn_rfc_pd_av,
+ trn_rfc_ph_av => trn_rfc_ph_av,
+ trn_rcpl_streaming_n => trn_rcpl_streaming_n,
+
+ trn_td => trn_td,
+ trn_trem_n => trn_trem_n,
+ trn_tsof_n => trn_tsof_n,
+ trn_teof_n => trn_teof_n,
+ trn_tsrc_dsc_n => trn_tsrc_dsc_n,
+ trn_tsrc_rdy_n => trn_tsrc_rdy_n,
+ trn_tdst_dsc_n => trn_tdst_dsc_n,
+ trn_tdst_rdy_n => trn_tdst_rdy_n,
+ trn_terrfwd_n => trn_terrfwd_n,
+ trn_tbuf_av => trn_tbuf_av,
+
+ cfg_do => cfg_do,
+ cfg_rd_wr_done_n => cfg_rd_wr_done_n,
+ cfg_di => cfg_di,
+ cfg_byte_en_n => cfg_byte_en_n,
+ cfg_dwaddr => cfg_dwaddr,
+ cfg_wr_en_n => cfg_wr_en_n,
+ cfg_rd_en_n => cfg_rd_en_n,
+
+ cfg_err_cor_n => cfg_err_cor_n,
+ cfg_err_cpl_abort_n => cfg_err_cpl_abort_n,
+ cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n,
+ cfg_err_cpl_unexpect_n => cfg_err_cpl_unexpect_n,
+ cfg_err_ecrc_n => cfg_err_ecrc_n,
+ cfg_err_posted_n => cfg_err_posted_n,
+ cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
+ cfg_err_ur_n => cfg_err_ur_n,
+ cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
+ cfg_err_locked_n => cfg_err_locked_n,
+ cfg_interrupt_n => cfg_interrupt_n,
+ cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
+ cfg_pm_wake_n => cfg_pm_wake_n,
+ cfg_pcie_link_state_n => cfg_pcie_link_state_n,
+ cfg_to_turnoff_n => cfg_to_turnoff_n,
+ cfg_interrupt_assert_n => cfg_interrupt_assert_n,
+ cfg_interrupt_di => cfg_interrupt_di,
+ cfg_interrupt_do => cfg_interrupt_do,
+ cfg_interrupt_mmenable => cfg_interrupt_mmenable,
+ cfg_interrupt_msienable => cfg_interrupt_msienable,
+
+ cfg_trn_pending_n => cfg_trn_pending_n,
+ cfg_bus_number => cfg_bus_number,
+ cfg_device_number => cfg_device_number,
+ cfg_function_number => cfg_function_number,
+ cfg_status => cfg_status,
+ cfg_command => cfg_command,
+ cfg_dstatus => cfg_dstatus,
+ cfg_dcommand => cfg_dcommand,
+ cfg_lstatus => cfg_lstatus,
+ cfg_lcommand => cfg_lcommand,
+ cfg_dsn => cfg_dsn,
+
+ fast_train_simulation_only => '0'
+ );
+
+ clk125 <= trn_clk;
+ reset125 <= not trn_reset_n;
+
+ rx_frame <= trn_rd;
+ rx_sof <= not trn_rsof_n;
+ rx_eof <= not trn_reof_n;
+ rx_valid <= not trn_rsrc_rdy_n;
+
+ trn_td <= tx_frame;
+ trn_tsof_n <= not tx_sof;
+ trn_teof_n <= not tx_eof;
+ trn_tsrc_rdy_n <= not tx_valid;
+ trn_trem_n <= x"0F" when tx_half = '1' else x"00";
+
+ tx_ready <= not trn_tdst_rdy_n;
+
+ bus_dev_func <= cfg_bus_number & cfg_device_number & cfg_function_number;
+
+ max_read <= cfg_dcommand(14 downto 12);
+ max_write <= cfg_dcommand(7 downto 5);
+
+ bar0 <= not trn_rbar_hit_n(0);
+end arch;
+