Add the linux device driver and netfpga files

This adds the device driver and netfpga files from the master thesis
(in Dutch) "Implementatie van de Recursive Internet Architecture op
een FPGA platform" by Alexander D'hoore.

1 files changed, 96 insertions, 0 deletions

diff --git a/netfpga10g/hdl/tx_eth.vhd b/netfpga10g/hdl/tx_eth.vhd
new file mode 100644
index 0000000..fab9cac
--- /dev/null
+++ b/netfpga10g/hdl/tx_eth.vhd
@@ -0,0 +1,96 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity tx_eth is port (
+        clk : in std_logic;
+        reset : in  std_logic;
+
+        xgmii_txd : out std_logic_vector(63 downto 0);
+        xgmii_txc : out std_logic_vector(7 downto 0);
+
+        tx_data : in std_logic_vector(63 downto 0);
+        tx_start : in std_logic;
+        tx_end : in std_logic;
+        tx_rem : in integer range 0 to 7;
+        
+        start_count_out : out std_logic_vector(31 downto 0);
+        end_count_out : out std_logic_vector(31 downto 0)
+);
+end tx_eth;
+
+architecture arch of tx_eth is
+        constant IDLE : std_logic_vector(7 downto 0) := x"07";
+        constant START : std_logic_vector(7 downto 0) := x"FB";
+        constant TERMINATE : std_logic_vector(7 downto 0) := x"FD";
+
+        constant PREAMBLE : std_logic_vector(7 downto 0) := "01010101";
+        constant SFD : std_logic_vector(7 downto 0) := "11010101";
+
+        type lanes_t is array (0 to 7) of std_logic_vector(7 downto 0);
+        signal lanes : lanes_t;
+
+        signal in_packet : std_logic;
+
+        signal start_count : unsigned(31 downto 0);
+        signal end_count : unsigned(31 downto 0);
+begin
+        start_count_out <= std_logic_vector(start_count);
+        end_count_out <= std_logic_vector(end_count);
+
+        tx_lanes_gen : for i in 0 to 7 generate
+                xgmii_txd(7+8*i downto 8*i) <= lanes(i);
+        end generate tx_lanes_gen;
+
+        tx_logic : process (clk, reset) begin
+                if reset = '1' then
+                        in_packet <= '0';
+                        start_count <= (others => '0');
+                        end_count <= (others => '0');
+
+                        for i in 0 to 7 loop
+                                lanes(i) <= IDLE;
+                                xgmii_txc(i) <= '1';
+                        end loop;
+
+                elsif rising_edge(clk) then
+                        for i in 0 to 7 loop
+                                lanes(i) <= IDLE;
+                                xgmii_txc(i) <= '1';
+                        end loop;
+
+                        if tx_start = '1' then
+                                in_packet <= '1';
+                                lanes(0) <= START;
+                                xgmii_txc(0) <= '1';
+                                lanes(1 to 6) <= (others => PREAMBLE);
+                                xgmii_txc(6 downto 1) <= (others => '0');
+                                lanes(7) <= SFD;
+                                xgmii_txc(7) <= '0';
+                                start_count <= start_count + 1;
+
+                        elsif tx_end = '1' then
+                                in_packet <= '0';
+                                end_count <= end_count + 1;
+
+                                for i in 0 to 7 loop
+                                        if i < tx_rem then
+                                                lanes(i) <= tx_data(63-8*i downto 56-8*i);
+                                                xgmii_txc(i) <= '0';
+                                        elsif i = tx_rem then
+                                                lanes(i) <= TERMINATE;
+                                                xgmii_txc(i) <= '1';
+                                        end if;
+                                end loop;
+
+                        elsif in_packet = '1' then
+                                for i in 0 to 7 loop
+                                        lanes(i) <= tx_data(63-8*i downto 56-8*i);
+                                        xgmii_txc(i) <= '0';
+                                end loop;
+                        end if;
+                end if;
+        end process;
+end arch;
+