1 files changed, 126 insertions, 0 deletions
diff --git a/netfpga10g/tests/eth_tx_test.vhd b/netfpga10g/tests/eth_tx_test.vhd
new file mode 100644
index 0000000..0697b84
--- /dev/null
+++ b/netfpga10g/tests/eth_tx_test.vhd
@@ -0,0 +1,126 @@
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+ 
+ENTITY eth_tx_test IS
+END eth_tx_test;
+ 
+ARCHITECTURE behavior OF eth_tx_test IS 
+
+        -- Component Declaration for the Unit Under Test (UUT)
+ 
+        COMPONENT eth_tx
+        PORT(
+         clk : IN  std_logic;
+         rd_en : OUT  std_logic;
+         rd_data : IN  std_logic_vector(63 downto 0);
+         rd_valid : IN  std_logic;
+         xgmii_txd : OUT  std_logic_vector(63 downto 0);
+         xgmii_txc : OUT  std_logic_vector(7 downto 0)
+        );
+        END COMPONENT;
+    
+        signal clk : std_logic := '0';
+        signal rd_en : std_logic;
+        signal rd_data : std_logic_vector(63 downto 0) := (others => '0');
+        signal rd_valid : std_logic := '0';
+
+        signal xgmii_txd : std_logic_vector(63 downto 0);
+        signal xgmii_txc : std_logic_vector(7 downto 0);
+
+        -- Clock period definitions
+        constant clk_period : time := 10 ns;
+
+        signal test_fail : std_logic := '0';
+   
+        constant IDLE : std_logic_vector(7 downto 0) := x"07";
+        constant START : std_logic_vector(7 downto 0) := x"FB";
+        constant TERM : std_logic_vector(7 downto 0) := x"FD";
+
+        constant PRE : std_logic_vector(7 downto 0) := "01010101";
+        constant SFD : std_logic_vector(7 downto 0) := "11010101";
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: eth_tx PORT MAP (
+          clk => clk,
+          rd_en => rd_en,
+          rd_data => rd_data,
+          rd_valid => rd_valid,
+          xgmii_txd => xgmii_txd,
+          xgmii_txc => xgmii_txc
+        );
+
+   -- Clock process definitions
+   clk_process :process
+   begin
+		clk <= '0';
+		wait for clk_period/2;
+		clk <= '1';
+		wait for clk_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin
+        for i in 1 to 5 loop
+        
+                if i = 1 or i = 2 then
+                        wait for clk_period;
+                                
+                        if rd_en /= '0' or
+                           xgmii_txd /= IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & IDLE or
+                           xgmii_txc /= "11111111" then
+                           test_fail <= '1';
+                        end if;
+                end if;
+                
+                rd_valid <= '1';
+                rd_data <= x"0123456789ABCDEF";
+                
+                wait for clk_period;
+                
+                if rd_en /= '1' or
+                   xgmii_txd /= SFD & PRE & PRE & PRE & PRE & PRE & PRE & START or
+                   xgmii_txc /= "00000001" then
+                   test_fail <= '1';
+                end if;
+                
+                wait for clk_period;
+                
+                if rd_en /= '1' or
+                   xgmii_txd /= x"EFCDAB8967452301" or
+                   xgmii_txc /= "00000000" then
+                   test_fail <= '1';
+                end if;
+                
+                rd_valid <= '1';
+                rd_data <= x"BBBBBBBBBBBBBBBB";
+                
+                wait for clk_period;
+                
+                if rd_en /= '1' or
+                   xgmii_txd /= x"BBBBBBBBBBBBBBBB" or
+                   xgmii_txc /= "00000000" then
+                   test_fail <= '1';
+                end if;
+                
+                rd_valid <= '0';
+                rd_data <= x"0000000000000000";
+                
+                wait for clk_period;
+                
+                if rd_en /= '0' or
+                   xgmii_txd /= IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & IDLE & TERM or
+                   xgmii_txc /= "11111111" then
+                   test_fail <= '1';
+                end if;
+                
+        end loop;
+        
+        wait;
+   end process;
+
+END;