diff options
Diffstat (limited to 'netfpga10g/hdl/top.vhd')
| -rw-r--r-- | netfpga10g/hdl/top.vhd | 243 |
1 files changed, 243 insertions, 0 deletions
diff --git a/netfpga10g/hdl/top.vhd b/netfpga10g/hdl/top.vhd new file mode 100644 index 0000000..83a5002 --- /dev/null +++ b/netfpga10g/hdl/top.vhd @@ -0,0 +1,243 @@ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +Library UNISIM; +use UNISIM.vcomponents.all; + +entity top is port ( + led1 : out std_logic; + led2 : out std_logic; + led3 : out std_logic; + + pcie_clk_p : in std_logic; + pcie_clk_n : in std_logic; + clk25 : in std_logic; + clk100 : in std_logic; + + pci_exp_rxn : in std_logic_vector(7 downto 0); + pci_exp_rxp : in std_logic_vector(7 downto 0); + pci_exp_txn : out std_logic_vector(7 downto 0); + pci_exp_txp : out std_logic_vector(7 downto 0); + + mdio : inout std_logic; + mdc : out std_logic; + phy_reset_n : out std_logic; + + xaui0_clk_p : in std_logic; + xaui0_clk_n : in std_logic; + xaui0_tx_l0_p : out std_logic; + xaui0_tx_l0_n : out std_logic; + xaui0_tx_l1_p : out std_logic; + xaui0_tx_l1_n : out std_logic; + xaui0_tx_l2_p : out std_logic; + xaui0_tx_l2_n : out std_logic; + xaui0_tx_l3_p : out std_logic; + xaui0_tx_l3_n : out std_logic; + xaui0_rx_l0_p : in std_logic; + xaui0_rx_l0_n : in std_logic; + xaui0_rx_l1_p : in std_logic; + xaui0_rx_l1_n : in std_logic; + xaui0_rx_l2_p : in std_logic; + xaui0_rx_l2_n : in std_logic; + xaui0_rx_l3_p : in std_logic; + xaui0_rx_l3_n : in std_logic +); +end top; + +architecture arch of top is + signal clk125 : std_logic; + signal reset125 : std_logic; + + signal count25 : unsigned(6 downto 0) := (others => '0'); + signal reset25 : std_logic := '1'; + + signal clk50 : std_logic; + signal clk156 : std_logic; + + signal rx_frame : std_logic_vector(63 downto 0); + signal rx_sof : std_logic; + signal rx_eof : std_logic; + signal rx_valid : std_logic; + signal rx_bar0 : std_logic; + + signal tx_frame : std_logic_vector(63 downto 0); + signal tx_sof : std_logic; + signal tx_eof : std_logic; + signal tx_half : std_logic; + signal tx_valid : std_logic; + signal tx_ready : std_logic; + + signal interrupt : std_logic; + signal interrupt_rdy : std_logic; + + signal max_read : std_logic_vector(2 downto 0); + signal max_write : std_logic_vector(2 downto 0); + + signal local : std_logic_vector(15 downto 0); + + signal xgmii_rxd : std_logic_vector(63 downto 0); + signal xgmii_rxc : std_logic_vector(7 downto 0); + signal xgmii_txd : std_logic_vector(63 downto 0); + signal xgmii_txc : std_logic_vector(7 downto 0); + + signal mdio_command : std_logic_vector(0 to 27); + signal mdio_data : std_logic_vector(0 to 15); + signal mdio_enable : std_logic; + signal mdio_done : std_logic; + + signal mdio_in : std_logic; + signal mdio_out : std_logic; + signal mdio_Z : std_logic; +begin + led1 <= '1'; + led2 <= '0'; + led3 <= '1'; + + process (clk25) begin + if rising_edge(clk25) then + if count25 = 100 then + reset25 <= '0'; + else + count25 <= count25 + 1; + end if; + end if; + end process; + + process (clk100, reset125) begin + if reset125 = '1' then + clk50 <= '0'; + elsif rising_edge(clk100) then + clk50 <= not clk50; + end if; + end process; + + pcie_wrapper : entity work.pcie_wrapper port map ( + pcie_clk_p => pcie_clk_p, + pcie_clk_n => pcie_clk_n, + reset25 => reset25, + + clk125 => clk125, + reset125 => reset125, + + pci_exp_rxn => pci_exp_rxn, + pci_exp_rxp => pci_exp_rxp, + pci_exp_txn => pci_exp_txn, + pci_exp_txp => pci_exp_txp, + + rx_frame => rx_frame, + rx_sof => rx_sof, + rx_eof => rx_eof, + rx_valid => rx_valid, + + tx_frame => tx_frame, + tx_sof => tx_sof, + tx_eof => tx_eof, + tx_half => tx_half, + tx_valid => tx_valid, + tx_ready => tx_ready, + + bus_dev_func => local, + + max_read => max_read, + max_write => max_write, + + interrupt => interrupt, + interrupt_rdy => interrupt_rdy, + + bar0 => rx_bar0 + ); + + system_loop: entity work.system_loop port map ( + eth_clk => clk156, + pcie_clk => clk125, + + rx_frame => rx_frame, + rx_sof => rx_sof, + rx_eof => rx_eof, + rx_valid => rx_valid, + rx_bar0 => rx_bar0, + + tx_frame => tx_frame, + tx_sof => tx_sof, + tx_eof => tx_eof, + tx_half => tx_half, + tx_valid => tx_valid, + tx_ready => tx_ready, + + interrupt => interrupt, + interrupt_rdy => interrupt_rdy, + + max_read => max_read, + max_write => max_write, + + local => local, + + xgmii_rxd => xgmii_rxd, + xgmii_rxc => xgmii_rxc, + + xgmii_txd => xgmii_txd, + xgmii_txc => xgmii_txc, + + mdio_command => mdio_command, + mdio_data => mdio_data, + mdio_enable => mdio_enable, + mdio_done => mdio_done + ); + + xaui : entity work.xaui_top + generic map ( + REVERSE_LANES => '1' + ) + port map ( + dclk => clk50, + reset => reset125, + xgmii_txd => xgmii_txd, + xgmii_txc => xgmii_txc, + xgmii_rxd => xgmii_rxd, + xgmii_rxc => xgmii_rxc, + clk156_out => clk156, + refclk_p => xaui0_clk_p, + refclk_n => xaui0_clk_n, + xaui_tx_l0_p => xaui0_tx_l0_p, + xaui_tx_l0_n => xaui0_tx_l0_n, + xaui_tx_l1_p => xaui0_tx_l1_p, + xaui_tx_l1_n => xaui0_tx_l1_n, + xaui_tx_l2_p => xaui0_tx_l2_p, + xaui_tx_l2_n => xaui0_tx_l2_n, + xaui_tx_l3_p => xaui0_tx_l3_p, + xaui_tx_l3_n => xaui0_tx_l3_n, + xaui_rx_l0_p => xaui0_rx_l0_p, + xaui_rx_l0_n => xaui0_rx_l0_n, + xaui_rx_l1_p => xaui0_rx_l1_p, + xaui_rx_l1_n => xaui0_rx_l1_n, + xaui_rx_l2_p => xaui0_rx_l2_p, + xaui_rx_l2_n => xaui0_rx_l2_n, + xaui_rx_l3_p => xaui0_rx_l3_p, + xaui_rx_l3_n => xaui0_rx_l3_n + ); + + mdio_iobuf : IOBUF port map ( + O => mdio_in, + IO => mdio, + I => mdio_out, + T => mdio_Z + ); + + mdio_module : entity work.mdio port map ( + clk125 => clk125, + reset125 => reset125, + + command => mdio_command, + data_out => mdio_data, + enable => mdio_enable, + done => mdio_done, + + mdio_in => mdio_in, + mdio_out => mdio_out, + mdio_Z => mdio_Z, + mdc => mdc, + phy_reset_n => phy_reset_n + ); +end arch; |